In recent years, with the generational evolution in memory chips, not only the size of memory cells has undergone miniaturization but also the distance between memory cells has become shorter. As a result, however, inter-cell interference has been increasing. In that regard, usually, memory operations are performed according to an operation sequence that is aimed at preventing inter-cell interference. However, in a multivalued nonvolatile memory such as a multivalued NAND flash memory, in order to ensure a high degree of reliability, the operation sequence for data writing has become extremely complex. For that reason, in order to prevent inter-cell interference from occurring, it becomes necessary to adjust the operation sequence for data writing at a minute level. As a result, it may take an extremely long period of time to perform data writing. At the same time, in order to enhance the performance of memory operations, it is extremely important to achieve enhancement in the operation speed.